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[VHDL-FPGA-Verilog] ssram

Description: 同步静态RAM读写程序，可用作模块，已通过ISE12.4验证-Synchronous Static RAM read and write procedures, can be used as modules, have been verified by ISE12.4
Platform: | Size: 1024 | Author: koo | Hits:

[VHDL-FPGA-Verilog] Ram-block-code

Description: It is a VHDL code for Block RAM
Platform: | Size: 1024 | Author: Umair | Hits:

[VHDL-FPGA-Verilog] RAM

Description: ram code in VHDL with its test code
Platform: | Size: 110592 | Author: sab | Hits:

[VHDL-FPGA-Verilog] ram

Description: hi this is ram code in vhdl
Platform: | Size: 8192 | Author: mani | Hits:

[VHDL-FPGA-Verilog] 6soft_247MHz_channel

Description: lte上行信道解交织解复用: RTL: ack_addr_gen.vhd ack地址产生 data_addr_gen.vhd 数据地址产生 de_interl_mux_con_ctrl.vhd 控制单元 de_interl_mux_con_top.vhd 顶层 de_interl_mux_con_tt.vhd 测试平台 de_mux_ram.vhd ram deinterl_pack.vhd 变量定义 delay.vhd 延迟 delayb.vhd 延迟 input_buffer.vhd 输入控制 ri_addr_gen.vhd ri信息提取 ul_common_pack.vhd 变量定义 write_ram.vhd 解交织 deintlv_data.txt 数据源 deintlv_data_ack.txt ack信息源 deintlv_data_cqi.txt cqi信息源 deintlv_data_ri.txt ri信息源 sim_lib.tcl altera库编译 ue.tcl modelsim 脚本-upstream channel deinterleaving lte demultiplexing: RTL: ack_addr_gen.vhd ack address generation data_addr_gen.vhd data address generation control unit de_interl_mux_con_top.vhd de_interl_mux_con_ctrl.vhd top de_interl_mux_con_tt.vhd test platform de_mux_ram.vhd ram deinterl_pack.vhd delay variable definition delay.vhd delayb.vhd delay input_buffer.vhd input control information extraction ul_common_pack.vhd ri_addr_gen.vhd ri definition of a variable data source write_ram.vhd deinterleaving deintlv_data.txt deintlv_data_cqi.txt cqi deintlv_data_ack.txt ack information source information sources sources of information deintlv_data_ri.txt ri sim_lib. tcl altera library compile script ue.tcl modelsim
Platform: | Size: 200704 | Author: renliang | Hits:

[VHDL-FPGA-Verilog] 3Channel_CIS_Processor_with-VHDL.ZIP

Description: This usefull source for control CIS Sensor and has fallowed functions 1) Read image data frome 3channel 200dpi CIS Sensor 2)Encoder Sync Technoledge for more high resolution analiysys with shared the time divition 3)Psudo Video Ram Read by using Xilinx BRAM 4)MCU Bidirectioal data Transfer 5) ADC data Converting -This is usefull source for control CIS Sensor and has fallowed functions 1) Read image data frome 3channel 200dpi CIS Sensor 2)Encoder Sync Technoledge for more high resolution analiysys with shared the time divition 3)Psudo Video Ram Read by using Xilinx BRAM 4)MCU Bidirectioal data Transfer 5) ADC data Converting
Platform: | Size: 15360 | Author: jeong | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: single-port RAM in write-first mode. module raminfr (clk, we, en, addr, di, do) input clk input we input en input [4:0] addr input [3:0] di output [3:0] do reg [3:0] RAM [31:0] reg [4:0] read_addr always @(posedge clk) begin if (en) begin if (we) RAM[addr] <= di read_addr <= addr end end assign do = RAM[read_addr] endmodule -single-port RAM in write-first mode. module raminfr (clk, we, en, addr, di, do) input clk input we input en input [4:0] addr input [3:0] di output [3:0] do reg [3:0] RAM [31:0] reg [4:0] read_addr always @(posedge clk) begin if (en) begin if (we) RAM[addr] <= di read_addr <= addr end end assign do = RAM[read_addr] endmodule
Platform: | Size: 32768 | Author: chai | Hits:

[VHDL-FPGA-Verilog] module-Temperature

Description: DS18B20引脚功能 GND地，DQ数据总线，VDD电源电压 18B20共有三种形式的存储器资源，它们分别是： ROM 只读存储器，用于存放DS18B20ID编码，其前八位是单线系列编码，后面48位是芯片唯一的序列号，最后8位是以上56位的CRC码。DS18B20共64位ROM RAM 数据暂存器，数据掉电后丢失，共9个字节，每个字节8位，第1、2个字节是温度转换后的数据值信息，EEPROM 非易失性记忆体，用于存放长期需要保存的数据，上下限温度报警值和校验数据 -DS18B20 Function GND Ground pin, DQ data bus, VDD supply voltage 18B20 There are three forms of memory resources, they are: ROM read-only memory for storing DS18B20ID coding, the top eight single-family is encoded, followed by 48 is the chip serial number only, over the last eight is 56-bit CRC code. DS18B20 total of 64-bit ROM RAM data store, data loss after power-down, a total of 9 bytes, each byte 8-bit, 1, 2 bytes of temperature data converted value information, EEPROM non-volatile volatile memory for storage of long-term need to preserve data, upper and lower temperature alarm and calibration data
Platform: | Size: 9216 | Author: 袁亚楠 | Hits:

[VHDL-FPGA-Verilog] General-memory-VHDL-code-library

Description: 通用存储器VHDL代码库。fifo,ram寄存器的代码和测试模块。-General-purpose memory VHDL code base. fifo, ram register code and test modules.
Platform: | Size: 23552 | Author: 周鑫 | Hits:

[VHDL-FPGA-Verilog] cpu-and-ram

Description: 这是一个用VHDL语言写的简单带存储器的CPU设计，不涉及流水线设计，只是简单的利用QUARTUES II里的ram-This is a simple memory write VHDL CPU design, does not involve the assembly line design, simply use the ram in QUARTUES II
Platform: | Size: 1262592 | Author: 郭雅娟 | Hits:

[VHDL-FPGA-Verilog] cpldrealizing-DUALportRAM-vhdl

Description: 双端口RAM 实现对于RAM的同时读写操作-dualport ram with the VHDL to realize read or write the ram at the same time
Platform: | Size: 781312 | Author: 夏文瀚 | Hits:

[VHDL-FPGA-Verilog] CPU-with-VHDL-16-32

Description: 在quartus中运行的32位指令集的16位CPU程序，模块化设计，包括MBR, BR, MR, ACC, MAR, PC, IR, CU, ROM, RAM, ALU等模块-In the the quartus run 32 16-bit CPU instruction set procedures, modular design, including the MBR, BR, MR, the ACC, the MAR, the PC, the IR CU, the ROM, RAM, ALU and other modules
Platform: | Size: 1651712 | Author: | Hits:

[VHDL-FPGA-Verilog] ram

Description: SRAM 静态存储器 vhdl代码 计算机组成原理-SRAM is a memory
Platform: | Size: 1024 | Author: 马三 | Hits:

[VHDL-FPGA-Verilog] ram_controller-vhdl-code

Description: 存储器接口vhdl代码 包括ram flash -ram controller vhdl
Platform: | Size: 6075392 | Author: 韩solo | Hits:

[VHDL-FPGA-Verilog] RAM_BLOCK

Description: Ram block code in Verilog
Platform: | Size: 25600 | Author: M. Usman | Hits:

[Other] TEST_RAM2

Description: test ram. vhdl nexys2 ISE 13.1
Platform: | Size: 1024 | Author: nobitatk21 | Hits:

[VHDL-FPGA-Verilog] DUAL-PORT-RAM

Description: vhdl使用双口RAM，工程编译通过。编译工具QUARTUS 9.0。-vhdl using the dual-port RAM, compiled by engineering.
Platform: | Size: 3737600 | Author: asdasdasd | Hits:

[VHDL-FPGA-Verilog] vhdl-Language-routine-highlights

Description: 工程中常用的VHDL控制模块，包括三态门，SDRAM，FIFO，PLL，RAM，FIlter等模块，非常实用的工程代码-Control module of VHDL is commonly used in engineering, including the tri-state gate, SDRAM, FIFO, PLL, RAM, FIlter module, very practical engineering code
Platform: | Size: 291840 | Author: shujian | Hits:

[VHDL-FPGA-Verilog] VHDL-memory

Description: 存储器的VHDL描述，包括ROM,RAM,FIFO,stack等多种类型-design of memory by VHDL
Platform: | Size: 33792 | Author: zmz | Hits:

[Other] ram

Description: vhdl实现简单寄存器，没有那么复杂，上vhdl课编出来的，对学生比较好理解。-vhdl simple register
Platform: | Size: 1067008 | Author: 黄浩 | Hits:
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